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rev 1 september 2005 1/29 29 f c 0 0 2 3 1 v dd osc comp drain source 13 v uvlo logic security latch pwm latch ff ff r/s s q s r1 r2 r3 q oscillator overtemp. detector error amplifier _ + 0.5 v + _ 1.7 s delay 250 ns blanking current amplifier on/off 0.5v 1 v/a _ + + _ 4.5 v viper100-e smps primary i.c. general features adjustable switching frequency up to 200 khz current mode control soft start and shutdown control automatic burst mode operation in stand-by condition able to meet ?blue angel? norm (<1w total power consumption) internally trimmed zener reference undervoltage lock-out with hysteresis integrated start-up supply over-temperature protection low stand-by current adjustable current limitation block diagram description viper100-e, made using vipower m0 technology, combines on the same silicon chip a state-of-the- art pwm circuit together with an optimized, high voltage, vertical power mosfet (620v/ 3a). typical applications cover offline power supplies with a secondary power capability of 50w in wide range condition and 100w in single range or with doubler configuration. it is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode without extra components. type v dss i n r ds(on) viper100-e 620v 3 a 2.5 ? pentawatt hv pentawatt hv (022y) www.st.com
viper100-e 2/29 contents 1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 drain pin (integrated power mosfet drain): . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 source pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 v dd pin (power supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 compensation pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 osc pin (oscillator frequency): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 current mode topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.3 high voltage start-up current suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 external clock synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 primary peak current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.8 operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
viper100-e 3/29 6 electrical over stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 electrical over stress ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1 electrical data viper100-e 4/29 1 electrical data 1.1 maximum rating table 1. absolute maximum rating symbol parameter value unit v ds continuous drain-source voltage (t j = 25 to 125c) ?0.3 to 620 v i d maximum current internally limited a v dd supply voltage 0 to 15 v v osc voltage range input 0 to v dd v v comp voltage range input 0 to 5 v i comp maximum continuous current 2 ma v esd electrostatic discharge (r =1.5k ? ; c=100pf) 4000 v i d(ar) avalanche drain-source current, repetitive or not repetitive (tc=100c; pulse width limited by tj max; < 1%) 2a p tot power dissipation at t c = 25oc 82 w t j junction operating temperature internally limited c t stg storage temperature -65 to 150 c
viper100-e 1 electrical data 5/29 1.2 electrical characteristics t j = 25c; v dd = 13v, unless otherwise specified table 2. power section (1) on inductive load, clamped. table 3. supply section table 4. oscillator section symbol parameter test conditions min typ max unit bv ds drain-source voltage i d = 1ma; v comp = 0v 620 v i dss off-state drain current v comp = 0v; t j = 125c v ds = 620v 1ma r ds(on) static drain-source on resistance i d = 2a i d = 2a; t j = 100c 2.3 2.5 4.5 ? t f fall time i d = 0.2a; v in =300v (1) figure 7 100 ns t r rise time i d = 0.4a; v in = 300v (1) figure 7 50 ns c oss output capacitance v ds = 25v 150 pf symbol parameter test conditions min typ max unit i ddch start-up charging current v dd = 5v; v ds = 35v (see figure 6)(see figure 11) -2 ma i dd0 operating supply current v dd = 12v; f sw = 0khz (see figure 6) 12 16 ma i dd1 operating supply current v dd = 12v; f sw = 100khz 15.5 ma v dd = 12v; f sw = 200khz 19 ma v ddoff undervoltage shutdown (see figure 6) 7.5 8 9 v v ddon undervoltage reset (see figure 6) 11 12 v v ddhyst hysteresis start-up (see figure 6) 2.4 3 v symbol parameter test conditions? min typ max unit f sw oscillator frequency total variation r t =8.2k ? ; c t =2.4nf v dd =9 to 15v; with r t 1%; c t 5% (see figure 10)(see figure 14) 90 100 110 khz v osc ih oscillator peak voltage 7.1 v v osc il oscillator valley voltage 3.7 v
1 electrical data viper100-e 6/29 table 5. error amplifier section table 6. pwm comparator section table 7. shutdown and overtemperature section symbol parameter test conditions? min typ max unit v ddreg v dd regulation point i comp =0ma (see figure 5) 12.6 13 13.4 v ? v ddreg total variation t j =0 to 100c 2 % g bw unity gain bandwidth from input =v dd to output = v comp comp pin is open (see figure 15) 150 khz a vol open loop voltage gain comp pin is open (see figure 15) 45 52 db g m dc transconductance v comp =2.5v (see figure 5) 1.1 1.5 1.9 ma/v v complo output low level i comp =-400a; v dd =14v 0.2 v v comphi output high level i comp =400a; v dd =12v 4.5 v i complo output low current capability v comp =2.5v; v dd =14v -600 a i comphi output high current capability v comp =2.5v; v dd =12v 600 a symbol parameter test conditions? min typ max unit h id ? v comp / ? i dpeak v comp = 1 to 3 v 0.7 1 1.3 v/a v compoff v comp offset i dpeak = 10ma 0.5 v i dpeak peak current limitation v dd = 12v; comp pin open 3 4 5.3 a t d current sense delay to turn- off i d = 1a 250 ns t b blanking time 250 360 ns t on(min) minimum on time 350 1200 ns symbol parameter test conditions? min typ max unit v compth restart threshold (see figure 8) 0.5 v t dissu disable set up time (see figure 8) 1.7 5 s t tsd thermal shutdown temperature (see figure 8) 140 170 c t hyst thermal shutdown hysteresis (see figure 8) 40 c
viper100-e 2 thermal data 7/29 2 thermal data table 8. thermal data symbol parameter pentawatt hv unit r thjc thermal resistance junction-case max 1.4 c/w r thja thermal resistance ambient-case max 60 c/w
3 pin description viper100-e 8/29 3 pin description 3.1 drain pin (integrated power mosfet drain): integrated power mosfet drain pin. it provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. the device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, pcb stray inductance, and allowing a snubberless operation for low output power. 3.2 source pin: power mosfet source pin. primary side circuit common ground connection. 3.3 v dd pin (power supply): this pin provides two functions : it corresponds to the low voltage supply of the control part of the circuit. if v dd goes below 8v, the start-up current source is activated and the output power mosfet is switched off until the v dd voltage reaches 11v. during this phase, the internal current consumption is reduced, the v dd pin is sourcing a current of about 2ma and the comp pin is shorted to ground. after that, the current source is shut down, and the device tries to start up by switching again. this pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. in case of primary regulation, an internal 13v trimmed reference voltage is used to maintain v dd at 13v. for secondary regulation, a voltage between 8.5v and 12.5v will be put on v dd pin by transformer design, in order to stuck the output of the transconductance amplifier to the high state. the comp pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. note that any overvoltage due to regulation loop failure is still detect ed by the error amplifier through the v dd voltage, which cannot overpass 13v. the output voltage will be somewhat higher than the nominal one, but still under control. 3.4 compensation pin this pin provides two functions : it is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. its bandwidth can be easily adjusted to the needed value with usual components value. as stated above, secondary regulation configurations are also implemented through the comp pin. when the comp voltage is going below 0.5v, the shut-down of the circuit occurs, with a zero duty cycle for the power mosfet. this feature can be used to switch off the converter, and is automatically activated by the regulation loop (no matter what the configuration is) to provide a burst mode operation in case of negligible output power or open load condition.
viper100-e 3 pin description 9/29 3.5 osc pin (oscillator frequency): an r t -c t network must be connected on that to define the switching frequency. note that despite the connection of r t to v dd , no significant frequency change occurs for v dd varying from 8v to 15v. it provides also a synchroni sation capability, when c onnected to an external frequency source. figure 1. connection diagrams (top view) figure 2. current and voltage convention pentawatt hv pentawatt hv (022y) - + 13v osc comp source drain vdd v comp v osc v dd v ds i comp i osc i dd i d fc00020
4 typical circuit viper100-e 10/29 4 typical circuit figure 3. offline power supply with auxiliary supply feedback figure 4. offline power supply with optocoupler feedback ac in +vcc gnd f1 br1 d3 r9 c1 r7 c4 c2 tr2 r1 c3 d1 d2 c10 tr1 c9 c7 l2 r3 c6 c5 r2 u1 viper100 - + 13v osc comp source drain vdd fc00081 c11 fc00091 ac in f1 br1 d3 r9 c1 r7 c4 c2 tr2 r1 c3 d1 d2 c10 tr1 c9 c7 l2 +vcc gnd c8 c5 r2 u1 viper100 u2 r4 r5 iso1 r6 r3 c6 - + 13v osc comp source drain vdd c11
viper100-e 5 operation description 11/29 5 operation description 5.1 current mode topology: the current mode control method, like the one integrated in the viper100-e, uses two control loops - an inner current control loop and an outer loop for voltage control. when the power mosfet output transistor is on, the inductor current (primary side of the transformer) is monitored with a sensefet technique and converted into a voltage v s proportional to this current. when v s reaches v comp (the amplified output voltage error) the power switch is switched off. thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. excellent open loop d.c. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. this results in improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. current mode topology also ensures good limitation in case there is a short circuit. during the first phase the output current increases slowly following the dynamic of the regulation loop. then it reaches the maximum limitation current internally set and finally stops because the power supply on v dd is no longer correct. for specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the comp pin. an integrated blanking filter inhibits the pwm comparator output for a short time after the integrated power mosfet is switched on. this function prevents anomalous or premature termination of the switching pulse in case there are current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. 5.2 stand-by mode stand-by operation in nearly open load conditions automatically leads to a burst mode operation allowing voltage regulation on the secondary side. the transition from normal operation to burst mode operation happens for a power p stby given by : where: l p is the primary inductance of the transformer. f sw is the normal switching frequency. i stby is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. this current can be computed as : t b + t d is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. note: that pstby may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. p stby 1 2 -- -l p i 2 stby f sw = i stby t b t d + () v in l p ----------------------------- =
5 operation description viper100-e 12/29 as soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13v regulation level, forcing the output voltage of the transconductance amplifier to low state (v comp < v compth ). this situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle. as soon as v dd gets back to the regulation level and the v compth threshold is reached, the device operates again. the a bove cycle repeats indefinit ely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. the equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main supply lines. this mode of operation allows the viper100-e to meet the new german "blue angel" norm with less than 1w total power consumption for the system when working in stand-by mode. the output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. the amplitude of this ripple is low, because of the output capacitors and low output current drawn in such conditions.the normal operation resumes automatically when the power gets back to higher levels than p stby . 5.3 high voltage start-up current suorce an integrated high voltage current source provides a bias current from the drain pin during the start-up phase. this current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the v dd pin. as soon as the voltage on this pin reaches the high voltage threshold v ddon of the uvlo logic, the device becomes active mode and starts switching. the start-up current generator is switched off, and the converter should normally provide the needed current on the v dd pin through the auxiliary winding of the transformer, as shown on (see figure 11) . in case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the v dd pin (i.e. short circuit on the output of the converter), the external capacitor discharges to the low threshold voltage v ddoff of the uvlo logic, and the device goes back to the inactive state where the internal circuits are in standby mode and the start-up current source is activated. the converter enters a endless start-up cycle, with a start- up duty cycle defined by the ratio of charging current towards discharging when the viper100- e tries to start. this ratio is fixed by design to 2a to 15a, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6w, for a 230vrms input voltage. this low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the transformer when a short circuit occurs. the external capacitor c vdd on the v dd pin must be sized according to the time needed by the converter to start up, when the device starts switching. this time t ss depends on many parameters, among which transformer design, output capacitors, soft start feature, and compensation network implemented on the comp pin. the following formula can be used for defining the minimum capacitor needed: where: i dd is the consumption current on the v dd pin when switching. refer to specified i dd1 and i dd 2 values. t ss is the start up time of the converter when the device begins to switch. worst case is generally at full load. c vdd i dd t ss v ddhyst -------------------- >
viper100-e 5 operation description 13/29 v ddhyst is the voltage hysteresis of the uvlo logic (refer to the minimum specified value). the soft start feature can be implemented on the comp pin through a simple capacitor which will be also used as the compensation network. in this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. in case a large regulation loop bandwidth is mandatory, the schematics of (see figure 17) can be used. it mixes a high performance compensation network together with a separate high value soft start capacitor. both soft start time and regulation loop bandwidth can be adjusted separately. if the device is intentionally shut down by tying the comp pin to ground, the device is also performing start-up cycles, and the v dd voltage is oscillating between v ddon and v ddoff . this voltage can be used for supplying external functions, provided that their consumption does not exceed 0.5ma. (see figure 18) shows a typical application of this function, with a latched shutdown. once the "shutdown" signal has been activated, the device remains in the off state until the input voltage is removed. 5.4 transconductance error amplifier the viper100-e includes a transconductance error amplifier. transconductance gm is the change in output current (i comp ) versus change in input voltage (v dd ). thus: the output impedance z comp at the output of this amplifier (comp pin) can be defined as: this last equation shows that the open loop gain a vol can be related to g m and z comp : a vol = g m x z comp where g m value for viper100-e is 1.5 ma/v typically. g m is defined by specification, but z comp and therefore a vol are subject to large tolerances. an impedance z can be connected between the comp pin and ground in order to define the transfer function f of the error amplifier more accurately, according to the following equation (very similar to the one above): f (s) = gm x z(s) the error amplifier frequency response is reported in figure 10. for different values of a simple resistance connected on the comp pin. the unloaded transconductance error amplifier shows an internal z comp of about 330k ? . more complex impedance can be connected on the comp pin to achieve different compensation level. a capacitor will provide an integrator function, thus eliminating the dc static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin . this configuration is illustrated in figure 20 as shown in figure 19 an additional noise filtering capacitor of 2.2nf is generally needed to avoid any high frequency interference. is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. figure 21 shows such a configuration. note: r1 and c2 build the classical compensation network, and q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. g m ? l comp ? v dd ------------------ - = z comp ? v comp ? i comp -------------------- - 1 g m ------- - ? v comp ? v dd ------------------------ - = =
5 operation description viper100-e 14/29 5.5 external clock synchronization: the osc pin provides a synchronisation capability when connected to an external frequency source. figure 21 shows one possible schematic to be adapted, depending the specific needs. if the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. the optocoupler must be able to provide 20ma through the optotransistor. 5.6 primary peak current limitation the primary i dpeak current and, consequently, the output power can be limited using the simple circuit shown in figure 22 . the circuit based on q1, r 1 and r 2 clamps the voltage on the comp pin in order to limit the primary peak current of the device to a value: where: the suggested value for r 1 +r 2 is in the range of 220k ? . 5.7 over-temperature protection over-temperature protection is based on chip temperature sensing. the minimum junction temperature at which over-temperature cut-out occurs is 140oc, while the typical value is 170oc. the device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40oc below the shutdown value (see figure 13) i dpeak v comp 0.5 ? h id ------------------------------- - = v comp 0.6 r 1 r 2 + r 2 ------------------ - =
viper100-e 5 operation description 15/29 5.8 operation pictures figure 5. v dd regulation point figure 6. undervoltage lockout figure 7. transition time figure 8. shutdown action figure 9. breakdown voltage vs. temperature figure 10. typical frequency variation i comp i comphi i complo v ddr eg 0 v dd slope = gm in ma/v fc00150 v ddon i ddch i dd0 v d d v ddoff v ds = 35 v fsw = 0 i dd v ddhyst fc00170 i d v ds t t tf tr 10% ipeak 10% v d 90% v d fc00160 vcomp vosc id t tdissu t t enable disable enable v compth fc0006 0 temperature (c) fc00180 0 20406080100120 0.95 1 1.05 1.1 1.15 bv dss ( normalized) temperature (c) 0 20 40 60 80 100 120 140 -5 -4 -3 -2 -1 0 1 fc00190 ( %)
5 operation description viper100-e 16/29 figure 11. behaviour of the high voltage current source at start-up figure 12. start-up waveforms ref. undervoltage lock out logic 15 ma 1 ma 3 ma 2 ma 15 ma vdd drain sourc e viper100 auxiliary primary winding vdd t v ddoff vddon start up duty cycle ~ 12% c vdd fc00100
viper100-e 5 operation description 17/29 figure 13. over-temperature protection sc 101 91 t j t tsd -t h yst t ts c v dd v dd on v dd off i d v co m p t t t t
5 operation description viper100-e 18/29 figure 14. oscillator rt c t osc vdd ~360 ? clk fc00050 c t fs w 40khz 15nf 22nf forbidden area forbidden area ct(nf) = fsw(khz) 880 1 2 3 5 10 20 30 50 30 50 100 200 300 500 1,000 rt (k ? ) frequency (khz) oscillator frequency vs rt and ct ct = 1.5 nf ct = 2.7 nf ct = 4.7 nf ct = 10 nf fc00030 fc00030 for r t > 1.2k ? and c t 40khz f sw 2.3 r t c t ---------- -1 550 r t 150 ? ------------------- - ? ?? ?? ? =
viper100-e 5 operation description 19/29 figure 15. error amplifier frequency response figure 16. error amplifier phase response 0.001 0.01 0.1 1 10 100 1,00 0 (20) 0 20 40 60 frequency (khz) voltage gain (db) rcomp = + rcomp = 270k rcomp = 82k rcomp = 27k rcomp = 12k fc00200 0.001 0.01 0.1 1 10 100 1,00 0 (50) 0 50 100 150 200 frequency (khz) phase () rcomp = + rcomp = 270k rcomp = 82k rcomp = 27k rcomp = 12k fc00210
5 operation description viper100-e 20/29 figure 17. mixed soft start and compensation figure 18. latched shut down figure 19. typical compensation network figure 20. slope compensation figure 21. external clock sinchronisation figure 22. current limitation circuit example auxiliar y winding - + 13v osc comp source drain vdd u1 viper100 r1 c1 + c2 d1 r2 r3 d2 d3 + c3 fc00131 c4 - + 13v osc comp source drain vdd viper100 shutdown u1 q1 q2 r1 r2 r3 r4 d1 fc00110 - + 13v osc comp source drain vdd viper100 u1 r1 c1 fc00121 c2 fc00141 - + 13v osc comp source drain vdd viper100 r1 r2 q1 c2 c1 r3 u1 c3 - + 13v osc comp source drain vdd u1 viper100 10 k ? fc00220 - + 13v osc comp source drain vdd viper100 u1 r1 r2 q1 fc00240
viper100-e 6 electrical over stress 21/29 6 electrical over stress 6.1 electrical over stress ruggedness the viper may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. following the layout considerations is sufficient to prevent catastrophic damages most of the time. however in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the v dd pin absolute maximum rating voltage value. such events may trigger the v dd internal protection circuitry which could be damaged by the strong discharge current of the v dd bulk capacitor. the simple rc filter shown in figure 23 can be implemented to improve the application immunity to such surges. figure 23. input voltage surges protection c1 b ulk capacitor d1 r1 (optional) c2 22nf auxilliary windin g 13v osc comp source drain vdd - + viperxx0 r2 39r
7 layout viper100-e 22/29 7 layout 7.1 layout considerations some simple rules insure a correct running of switching power supplies. they may be classified into two categories: ? minimizing power loops: the switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. this avoids radiated emc noises, conducted emc noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. ? using different tracks for low level and power signals: interference due to mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (input overvoltages, output short circuits...). in case of viper, these rules apply as shown on (see figure 24) . ? loops c1-t1-u1, c5-d2-t1, and c7-d1-t1 must be minimized. ? c6 must be as close as possible to t1. ? signal components c2, iso1, c3, and c4 are using a dedicated track connected directly to the power source of the device. figure 24. recommended layout t1 u1 viperxx0 13v osc comp source drain vdd - + c4 c2 c5 c1 d2 r1 r2 d1 c7 c6 c3 iso1 fr om input d iodes bridge to secondar y filtering and loa d fc00500
viper100-e 8 package mechanical data 23/29 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
8 package mechanical data viper100-e 24/29 pentawatt hv mechanical data dim mm. inch min. typ. maw. min. typ. max. a 4.30 4.80 0.169 0.189 c 1.17 1.37 0.046 0.054 d 2.40 2.80 0.094 0.11 e 0.35 0.55 0.014 0.022 f 0.60 0.80 0.024 0.031 g1 4.91 5.21 0.193 0.205 g2 7.49 7.80 0.295 0.307 h1 9.30 9.70 0.366 0.382 h2 10.40 0.409 h3 10.05 10.40 0.396 0.409 l 15.60 17.30 6.14 0.681 l1 14.60 15.22 0.575 0.599 l2 21.20 21.85 0.835 0.860 l3 22.20 22.82 0.874 0.898 l5 2.60 3 0.102 0.118 l6 15.10 15.80 0.594 0.622 l7 6 6.60 0.236 0.260 m 2.50 3.10 0.098 0.122 m1 4.50 5.60 0.177 0.220 r0.50 0.02 v4 90 diam 3.65 3.85 0.144 0.152 p023h3
viper100-e 8 package mechanical data 25/29 pentawatt hv 022y ( vertical high pitch ) mechanical data dim mm. inch min. typ. maw. min. typ. max. a 4.30 4.80 0.169 0.189 c 1.17 1.37 0.046 0.054 d 2.40 2.80 0.094 0.110 e 0.35 0.55 0.014 0.022 f 0.60 0.80 0.024 0.031 g1 4.91 5.21 0.193 0.205 g2 7.49 7.80 0.295 0.307 h1 9.30 9.70 0.366 0.382 h2 10.40 0.409 h3 10.05 10.40 0.396 0.409 l 16.42 17.42 0.646 0.686 l1 14.60 15.22 0.575 0.599 l3 20.52 21.52 0.808 0.847 l5 2.60 3.00 0.102 0.118 l6 15.10 15.80 0.594 0.622 l7 6.00 6.60 0.236 0.260 m 2.50 3.10 0.098 0.122 m1 5.00 5.70 0.197 0.224 r 0.50 0.02 0.020 v4 90 90 diam 3.65 3.85 0.144 0.154 a c h2 h3 h1 l5 dia l3 l6 l7 f g1 g2 l l1 d r m m1 e resin between leads v4
8 package mechanical data viper100-e 26/29 figure 25. pentawatt hv tube shipment ( no suffix ) all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5 ) 532 a 18 b 33.1 c ( 0.1 ) 1
viper100-e 9 order codes 27/29 9 order codes pentawatt hv pentawatt hv (022y) viper100-e VIPER100-22-E
10 revision history viper100-e 28/29 10 revision history date revision changes 23-sep-2005 1 initial release.
viper100-e 10 revision history 29/29 i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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